Initial QSfera import
This commit is contained in:
Курнат Андрей
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package arm
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import (
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"github.com/segmentio/asm/cpu/cpuid"
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. "golang.org/x/sys/cpu"
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)
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type CPU cpuid.CPU
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func (cpu CPU) Has(feature Feature) bool {
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return cpuid.CPU(cpu).Has(cpuid.Feature(feature))
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}
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func (cpu *CPU) set(feature Feature, enable bool) {
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(*cpuid.CPU)(cpu).Set(cpuid.Feature(feature), enable)
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}
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type Feature cpuid.Feature
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const (
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SWP Feature = 1 << iota // SWP instruction support
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HALF // Half-word load and store support
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THUMB // ARM Thumb instruction set
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BIT26 // Address space limited to 26-bits
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FASTMUL // 32-bit operand, 64-bit result multiplication support
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FPA // Floating point arithmetic support
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VFP // Vector floating point support
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EDSP // DSP Extensions support
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JAVA // Java instruction set
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IWMMXT // Intel Wireless MMX technology support
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CRUNCH // MaverickCrunch context switching and handling
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THUMBEE // Thumb EE instruction set
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NEON // NEON instruction set
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VFPv3 // Vector floating point version 3 support
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VFPv3D16 // Vector floating point version 3 D8-D15
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TLS // Thread local storage support
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VFPv4 // Vector floating point version 4 support
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IDIVA // Integer divide instruction support in ARM mode
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IDIVT // Integer divide instruction support in Thumb mode
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VFPD32 // Vector floating point version 3 D15-D31
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LPAE // Large Physical Address Extensions
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EVTSTRM // Event stream support
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AES // AES hardware implementation
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PMULL // Polynomial multiplication instruction set
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SHA1 // SHA1 hardware implementation
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SHA2 // SHA2 hardware implementation
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CRC32 // CRC32 hardware implementation
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)
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func ABI() CPU {
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cpu := CPU(0)
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cpu.set(SWP, ARM.HasSWP)
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cpu.set(HALF, ARM.HasHALF)
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cpu.set(THUMB, ARM.HasTHUMB)
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cpu.set(BIT26, ARM.Has26BIT)
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cpu.set(FASTMUL, ARM.HasFASTMUL)
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cpu.set(FPA, ARM.HasFPA)
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cpu.set(VFP, ARM.HasVFP)
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cpu.set(EDSP, ARM.HasEDSP)
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cpu.set(JAVA, ARM.HasJAVA)
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cpu.set(IWMMXT, ARM.HasIWMMXT)
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cpu.set(CRUNCH, ARM.HasCRUNCH)
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cpu.set(THUMBEE, ARM.HasTHUMBEE)
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cpu.set(NEON, ARM.HasNEON)
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cpu.set(VFPv3, ARM.HasVFPv3)
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cpu.set(VFPv3D16, ARM.HasVFPv3D16)
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cpu.set(TLS, ARM.HasTLS)
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cpu.set(VFPv4, ARM.HasVFPv4)
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cpu.set(IDIVA, ARM.HasIDIVA)
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cpu.set(IDIVT, ARM.HasIDIVT)
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cpu.set(VFPD32, ARM.HasVFPD32)
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cpu.set(LPAE, ARM.HasLPAE)
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cpu.set(EVTSTRM, ARM.HasEVTSTRM)
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cpu.set(AES, ARM.HasAES)
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cpu.set(PMULL, ARM.HasPMULL)
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cpu.set(SHA1, ARM.HasSHA1)
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cpu.set(SHA2, ARM.HasSHA2)
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cpu.set(CRC32, ARM.HasCRC32)
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return cpu
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}
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+74
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package arm64
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import (
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"github.com/segmentio/asm/cpu/cpuid"
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. "golang.org/x/sys/cpu"
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)
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type CPU cpuid.CPU
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func (cpu CPU) Has(feature Feature) bool {
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return cpuid.CPU(cpu).Has(cpuid.Feature(feature))
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}
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func (cpu *CPU) set(feature Feature, enable bool) {
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(*cpuid.CPU)(cpu).Set(cpuid.Feature(feature), enable)
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}
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type Feature cpuid.Feature
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const (
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FP Feature = 1 << iota // Floating-point instruction set (always available)
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ASIMD // Advanced SIMD (always available)
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EVTSTRM // Event stream support
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AES // AES hardware implementation
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PMULL // Polynomial multiplication instruction set
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SHA1 // SHA1 hardware implementation
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SHA2 // SHA2 hardware implementation
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CRC32 // CRC32 hardware implementation
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ATOMICS // Atomic memory operation instruction set
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FPHP // Half precision floating-point instruction set
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ASIMDHP // Advanced SIMD half precision instruction set
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CPUID // CPUID identification scheme registers
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ASIMDRDM // Rounding double multiply add/subtract instruction set
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JSCVT // Javascript conversion from floating-point to integer
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FCMA // Floating-point multiplication and addition of complex numbers
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LRCPC // Release Consistent processor consistent support
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DCPOP // Persistent memory support
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SHA3 // SHA3 hardware implementation
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SM3 // SM3 hardware implementation
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SM4 // SM4 hardware implementation
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ASIMDDP // Advanced SIMD double precision instruction set
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SHA512 // SHA512 hardware implementation
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SVE // Scalable Vector Extensions
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ASIMDFHM // Advanced SIMD multiplication FP16 to FP32
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)
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func ABI() CPU {
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cpu := CPU(0)
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cpu.set(FP, ARM64.HasFP)
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cpu.set(ASIMD, ARM64.HasASIMD)
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cpu.set(EVTSTRM, ARM64.HasEVTSTRM)
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cpu.set(AES, ARM64.HasAES)
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cpu.set(PMULL, ARM64.HasPMULL)
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cpu.set(SHA1, ARM64.HasSHA1)
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cpu.set(SHA2, ARM64.HasSHA2)
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cpu.set(CRC32, ARM64.HasCRC32)
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cpu.set(ATOMICS, ARM64.HasATOMICS)
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cpu.set(FPHP, ARM64.HasFPHP)
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cpu.set(ASIMDHP, ARM64.HasASIMDHP)
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cpu.set(CPUID, ARM64.HasCPUID)
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cpu.set(ASIMDRDM, ARM64.HasASIMDRDM)
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cpu.set(JSCVT, ARM64.HasJSCVT)
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cpu.set(FCMA, ARM64.HasFCMA)
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cpu.set(LRCPC, ARM64.HasLRCPC)
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cpu.set(DCPOP, ARM64.HasDCPOP)
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cpu.set(SHA3, ARM64.HasSHA3)
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cpu.set(SM3, ARM64.HasSM3)
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cpu.set(SM4, ARM64.HasSM4)
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cpu.set(ASIMDDP, ARM64.HasASIMDDP)
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cpu.set(SHA512, ARM64.HasSHA512)
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cpu.set(SVE, ARM64.HasSVE)
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cpu.set(ASIMDFHM, ARM64.HasASIMDFHM)
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return cpu
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}
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+22
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// Pakage cpu provides APIs to detect CPU features available at runtime.
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package cpu
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import (
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"github.com/segmentio/asm/cpu/arm"
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"github.com/segmentio/asm/cpu/arm64"
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"github.com/segmentio/asm/cpu/x86"
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)
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var (
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// X86 is the bitset representing the set of the x86 instruction sets are
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// supported by the CPU.
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X86 = x86.ABI()
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// ARM is the bitset representing which parts of the arm instruction sets
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// are supported by the CPU.
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ARM = arm.ABI()
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// ARM64 is the bitset representing which parts of the arm64 instruction
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// sets are supported by the CPU.
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ARM64 = arm64.ABI()
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)
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+32
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// Package cpuid provides generic types used to represent CPU features supported
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// by the architecture.
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package cpuid
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// CPU is a bitset of feature flags representing the capabilities of various CPU
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// architeectures that this package provides optimized assembly routines for.
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//
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// The intent is to provide a stable ABI between the Go code that generate the
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// assembly, and the program that uses the library functions.
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type CPU uint64
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// Feature represents a single CPU feature.
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type Feature uint64
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const (
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// None is a Feature value that has no CPU features enabled.
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None Feature = 0
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// All is a Feature value that has all CPU features enabled.
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All Feature = 0xFFFFFFFFFFFFFFFF
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)
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func (cpu CPU) Has(feature Feature) bool {
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return (Feature(cpu) & feature) == feature
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}
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func (cpu *CPU) Set(feature Feature, enabled bool) {
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if enabled {
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*cpu |= CPU(feature)
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} else {
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*cpu &= ^CPU(feature)
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}
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}
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+76
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package x86
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import (
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"github.com/segmentio/asm/cpu/cpuid"
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. "golang.org/x/sys/cpu"
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)
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type CPU cpuid.CPU
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func (cpu CPU) Has(feature Feature) bool {
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return cpuid.CPU(cpu).Has(cpuid.Feature(feature))
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}
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func (cpu *CPU) set(feature Feature, enable bool) {
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(*cpuid.CPU)(cpu).Set(cpuid.Feature(feature), enable)
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}
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type Feature cpuid.Feature
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const (
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SSE Feature = 1 << iota // SSE functions
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SSE2 // P4 SSE functions
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SSE3 // Prescott SSE3 functions
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SSE41 // Penryn SSE4.1 functions
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SSE42 // Nehalem SSE4.2 functions
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SSE4A // AMD Barcelona microarchitecture SSE4a instructions
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SSSE3 // Conroe SSSE3 functions
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AVX // AVX functions
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AVX2 // AVX2 functions
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AVX512BF16 // AVX-512 BFLOAT16 Instructions
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AVX512BITALG // AVX-512 Bit Algorithms
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AVX512BW // AVX-512 Byte and Word Instructions
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AVX512CD // AVX-512 Conflict Detection Instructions
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AVX512DQ // AVX-512 Doubleword and Quadword Instructions
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AVX512ER // AVX-512 Exponential and Reciprocal Instructions
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AVX512F // AVX-512 Foundation
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AVX512IFMA // AVX-512 Integer Fused Multiply-Add Instructions
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AVX512PF // AVX-512 Prefetch Instructions
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AVX512VBMI // AVX-512 Vector Bit Manipulation Instructions
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AVX512VBMI2 // AVX-512 Vector Bit Manipulation Instructions, Version 2
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AVX512VL // AVX-512 Vector Length Extensions
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AVX512VNNI // AVX-512 Vector Neural Network Instructions
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AVX512VP2INTERSECT // AVX-512 Intersect for D/Q
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AVX512VPOPCNTDQ // AVX-512 Vector Population Count Doubleword and Quadword
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CMOV // Conditional move
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)
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func ABI() CPU {
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cpu := CPU(0)
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cpu.set(SSE, true) // TODO: golang.org/x/sys/cpu assumes all CPUs have SEE?
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cpu.set(SSE2, X86.HasSSE2)
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cpu.set(SSE3, X86.HasSSE3)
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cpu.set(SSE41, X86.HasSSE41)
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cpu.set(SSE42, X86.HasSSE42)
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cpu.set(SSE4A, false) // TODO: add upstream support in golang.org/x/sys/cpu?
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cpu.set(SSSE3, X86.HasSSSE3)
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cpu.set(AVX, X86.HasAVX)
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cpu.set(AVX2, X86.HasAVX2)
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cpu.set(AVX512BF16, X86.HasAVX512BF16)
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cpu.set(AVX512BITALG, X86.HasAVX512BITALG)
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cpu.set(AVX512BW, X86.HasAVX512BW)
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cpu.set(AVX512CD, X86.HasAVX512CD)
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cpu.set(AVX512DQ, X86.HasAVX512DQ)
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cpu.set(AVX512ER, X86.HasAVX512ER)
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cpu.set(AVX512F, X86.HasAVX512F)
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cpu.set(AVX512IFMA, X86.HasAVX512IFMA)
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cpu.set(AVX512PF, X86.HasAVX512PF)
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cpu.set(AVX512VBMI, X86.HasAVX512VBMI)
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cpu.set(AVX512VBMI2, X86.HasAVX512VBMI2)
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cpu.set(AVX512VL, X86.HasAVX512VL)
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cpu.set(AVX512VNNI, X86.HasAVX512VNNI)
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cpu.set(AVX512VP2INTERSECT, false) // TODO: add upstream support in golang.org/x/sys/cpu?
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cpu.set(AVX512VPOPCNTDQ, X86.HasAVX512VPOPCNTDQ)
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cpu.set(CMOV, true) // TODO: golang.org/x/sys/cpu assumes all CPUs have CMOV?
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return cpu
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}
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